Job Position : Lead Engineer- Asic/ Soc Physical Design
Job Location : Bengaluru/Bangalore, Noida, United States (U.S)
Job Description:
Leading a team of 2 to 5 members
Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS, block integration and ECO generation
Block level implementation from netlist to GDS
Handling timing closure of high frequency blocks
Handling blocks of high instance counts 1M instance and above
Expertise in signoff closure- Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
Understanding constraints and fixing techniques
Understanding SI prevention, fixing methodology and implementation
Proficient in layout edit techniques
Proficient in Synopsys ICC or Mentor Olympus and Atoptech tool set
Experience in Design Automation and UNIX system
Experience in Tcl/Tk, PERL is a plus
Job Requirements :
Experience level 6 to 8 years
Must possess required hands on experience in handling block/chip level implementation from Netlist to GDS
Must possess hands on experience in timing closure and physical verification closure
Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
Experience in handling lower tech nodes that include 14nm, 28nm, 40nm using ICC or SOC Encounter tools
Ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time
Experience in Synthesis and Formal is a plus
Excellent verbal and written communication skills along with debug skills, analytical skills and the ability to work independently
Apply : pdjobs@smartplayin.com
SmartPlay Technologies is an established design services company with expertise in digital, analog, wireless software and system design. With a team of 1200+ employees and offices in Bangalore, Hyderabad, Noida, Chennai, Singapore, San Jose, San Diego and Austin, SmartPlay has emerged as one of the fastest growing technology services company in the world.
Job Location : Bengaluru/Bangalore, Noida, United States (U.S)
Job Description:
Leading a team of 2 to 5 members
Chip level floorplanning, partitioning, timing budget generation, powerplanning, top PnR, CTS, block integration and ECO generation
Block level implementation from netlist to GDS
Handling timing closure of high frequency blocks
Handling blocks of high instance counts 1M instance and above
Expertise in signoff closure- Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level
Understanding constraints and fixing techniques
Understanding SI prevention, fixing methodology and implementation
Proficient in layout edit techniques
Proficient in Synopsys ICC or Mentor Olympus and Atoptech tool set
Experience in Design Automation and UNIX system
Experience in Tcl/Tk, PERL is a plus
Job Requirements :
Experience level 6 to 8 years
Must possess required hands on experience in handling block/chip level implementation from Netlist to GDS
Must possess hands on experience in timing closure and physical verification closure
Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz
Experience in handling lower tech nodes that include 14nm, 28nm, 40nm using ICC or SOC Encounter tools
Ability to think on the spot for quick solutions and work-around at the time of tapeout to hit the schedule on time
Experience in Synthesis and Formal is a plus
Excellent verbal and written communication skills along with debug skills, analytical skills and the ability to work independently
Apply : pdjobs@smartplayin.com
SmartPlay Technologies is an established design services company with expertise in digital, analog, wireless software and system design. With a team of 1200+ employees and offices in Bangalore, Hyderabad, Noida, Chennai, Singapore, San Jose, San Diego and Austin, SmartPlay has emerged as one of the fastest growing technology services company in the world.
